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Micrel
MICRF405
 
 
 
 
April 2006 
16
M9999-041906
 (408) 955-1690
 
The sequence of a typically packet transfer is shown
in Figure 7.
1.   Set the 405 in transmit mode with the correct
settings by writing in the TX control word.
Once SEN is pulled high, the internal load will
activate the new settings. The 405 will now
start   the   PLL   and   turn   on   the   PA   (if
PA_LDc_en is set)
2.   Pull SEN low, and address the TX buffer.
Address=29+R/W, RW=0.
3.   Write the frame length into the data buffer. On
the 8
th
 falling edge of SCK, clocking in the last
bit, the modulation will start. If MOD_LDc_en is
not set, check that lock detect (LD) is high after
PA is turned on before writing last bit (or the
complete byte 3). If MOD_LDc_en=1, finish
steps 2 and 3 immediately after step 1. The
MICRF405 will now wait until the transmitter is
ready (PLL tuned in, PA on and LD high)
before starting to modulate. In either case, the
packet engine will start to transmit the desired
preamble   and   SyncID   bytes   once   the
modulation starts.
4.   When the last bit of the last SyncID byte is
being sent, the RDY signal is high. After the
falling edge of RDY, the packet engine is
sending the frame length, and the buffer is
then ready for refill. The time between 3 and 4
will vary depending, upon the bit rate and
desired number of bytes in the preamble and
SyncID field. The first RDY pulse will, however,
notify the user when to enter the 1
st
 byte of the
payload. Step four is repeated for all the bytes
in the payload, meaning [frame length 
number of CRC bytes] times. It is important
that the buffer is refilled after the falling edge of
RDY and before the next falling edge of RDY.
5.   In this step, all user data is received in the 405
and it transmits the last part of the packet. This
means that the SEN now can be pulled high at
any   time,   closing   the   write   session.   If
PA_LDc_en=1   and   load_en=1,   it   is   then
necessary to leave SEN low until the end of
packet. This is because raising SEN will
generate a load pulse, and this, in turn, causes
the PA_LDc function to turn off the PA for a
short period of time. The RDY signal will be
high when the last bit of the payload is being
sent, but there is now no need to refill the
buffer. Also, if CRC is enabled, then RDY will
be high during the last bit of each of the CRC
bytes being sent. Because of an internal
sampling the actual RF output lags 1 bit
period, which means the modulation will stop
one bit period after the last RDY pulse.
6.   The frame is now completely transmitted. If
PA_FEc_en=1, the PA will be automatically
turned off immediately after last bit in packet is
transmitted. The PLL will, however, remain
running. (This state is equal to MODE[1:0]=3
(TX),   PA_LDc_en=0   and   PA[2:0]=0.)   If
PA_FEc_en=0 the PA will remain on until it is
turned off by the MODE or PA bits. In step 6,
the buffer is ready for a new packet. Any 8bits
entered into the buffer in this sections is
though of as a new frame length, refer back to
Section 3. This, assuming the MICRF405
remains in TX (MODE[1:0]=3). In this case,
and when PA_FEc_en=1, the PA will be turned
on once the 8
th
  bit is clocked in. It is
recommended to use the MOD_LDc function in
this case as it will delay the modulation until
the PLL has stabilized after the PA is turned
on. If not the start of the modulation will be
distorted and may interfere the settling of the
PLL due to PA turn on (please see chapter
Lock Detect).
 
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